As is known, there is an increasing demand for memories characterized by flexibility, low power consumption, and immunity to noise. These characteristics are difficult to achieve simultaneously because each can only be obtained at the expense of the others. As such, a trade-off is inevitable, bearing in mind its effect in terms of technological yield, and the difficulty of achieving an all-round solution suitable for all applications.
A timer, for example, is useful in reducing power consumption, but being invariably rigid, it responds poorly to certain inevitable technological changes that are better catered to by a static type of architecture. Moreover, a timed architecture, though it provides for solving certain noise, dissipation and speed problems, is limited in situations where certain lines are slowly brought up to the steady-state condition.
Countless additional factors (e.g., slow storage locations, component characteristic shift, localized nonuniform behavior) also exist, and require specific measures to be taken to ensure adequate reliability of the memory.